Objectives

  • Perform a market research on memory applications to identify the potential applications the FB-DRAM cell could target. Since the new devices will demonstrate a peculiar behaviour compared to 1C-1T DRAM the scope of the market study should be wider.
  • Benchmark the technology information from WP1 and the electrical results from WP4.
  • Provide a product positioning for the different memory solutions proposed in the project.
  • Provide a detailed silicon evaluation report based on a test chip integrating multiple low power eDRAM instance sizes.
  • Provide a “margining report” with results of high sigma statistical simulations ran for a defined suite of key stability criteria.
  • Provide a compiler for low power eDRAM IP that can be licenced to customers in the target technology.
  • Describe with respect to the identified market the exploitation plans of the devices.

Role of partners

  • UGR, STM, CEA, GSS, KIST, SureCore: Perform a market research on memory applications to identify the potential applications the FB-DRAM cell could target.
  • UGR, INPG: Compare technology information from WP1 with the electrical results from WP4.
  • SureCore: Design, fabrication and evaluation of memory test chips. Provide a low power eDRAM IP that can be licensed to customers in the target technology.
  • KIST: Benchmarking with other alternatives.

Interaction with other WPs

  • Employs technology from WP1.
  • Employs models and tools from WP4.