Objectives

  • Provide the data to allow the final benchmarking of the cells on a test memory array.
  • Develop compact models based on analytical equations. This modelling will take into account the non-equilibrium of the body potential. It will describe both the static and dynamic behaviour of the drain current as a function of terminals bias for the different programming mechanisms of ‘0’- and ‘1’-states. It will target deep submicron devices in the temperature range of 25°C to 150°C and can be able, by iterations, to reproduce the behaviour of an entire memory matrix array.
  • Provide new or improved models of the leakage currents, governing the retention time and information loss.
  • Development of an advanced scalable and reliable physics-based semi-analytical model for the transient effects occurring in a wide range of programming voltages. The model will target nanometre-size devices with length from 25 nm down to 10 nm and thickness from 50 nm down to 5 nm. Extension of the model to high temperatures up to 150°C.
  • Development of parameter extraction procedures for compact models describing the programming injection mechanisms.
  • Validation of the compact and semi-analytical models by TCAD and Monte Carlo based simulations (WP3) and measurements (WP2).
  • Building a generic modular library of FB-DRAM elements, including a variety of injection, retention and reading mechanisms, to be used for implementation in a memory matrix array.
  • Designing memory arrays and circuits for embedded and stand-alone applications.

Role of partners

  • UGR: Semi-analytical modelling.
  • STM: Device building block library and advanced toolbox.
  • CEA: Develop compact models based on analytical equations.
  • INPG: Development of parameter extraction procedures for compact models describing the programming injection mechanisms.
  • GSS: Development of SPICE macro Compact models, development of uniform and statistical compact model approach, implementation of DRAM cell compact model into the PDK.
  • SureCore: Validation of design library in commercial EDA tool environment. Design of memory matrix.
  • KIST: Design of memory matrix.

Interaction with other WPs

  • Employ experimental results from WP2.
  • Employ simulation results from WP3.
  • Provide tools and building blocks for WP5.