Objectives

  • Experiment-based selection of the best suited FB-DRAM to compete or replace conventional bulk-Si DRAMs on the market place.
  • Development of specific methodologies for the extraction of FB-DRAM parameters.
  • Investigation of memory performance and scalability.
  • Extraction of the main electrical and technological parameters relevant for FB-DRAM process optimization and compact modelling.
  • Characterization-based selection of technology modules and ultra-scaled device architectures suitable for FB-DRAMs.
  • Comparison of processed FB-DRAM variants and selection of most promising device.
  • Experimental validation of TCAD numerical simulations, compact and semi-analytical models.
  • Exploration of suitable 1T-DRAM memory block architectures optimised for low voltage/low power operation.
  • Characterization of the designed and fabricated memory array.
  • Characterization of failure analysis.
  • Characterization of memory matrix.

Role of partners

  • UGR: Characterization and benchmarking of existing and optimized devices.
  • STM: On-wafer statistical measurements.
  • CEA: Characterization of FB-DRAM based on 3D Si nanowires.
  • INPG: Characterization and benchmarking of existing and optimized devices.
  • IBM: Characterization of III-V nanowires and devices.
  • SureCore: Functional characterization of the memory matrix.
  • KIST: Characterization of failure modes at extremely accelerating conditions.

Interaction with other WPs

  • Characterize devices fabricated in WP1, provide inputs for optimized devices.
  • Provide experimental data to WP3 to calibrate the numerical simulation.
  • Provide the necessary parameters to WP4 for compact and semi-analytical models and validate them. Characterization of the memory matrix from WP4
  • Provide inputs for memory specifications to WP5.