Objectives

  • Fabrication of the various FB-DRAM structures proposed in REMINDER. The fabrication comprises optimized memory bit cells, optimized memory matrix, and a memory demonstrator.
  • Analysis of the advanced process modules which must be developed for all solutions, and the evaluation of the corresponding technological risk.
  • Development of specific engineering modules will thus be realized taking into account compatibility with CMOS process and technological risk in FD28 and FD14 STM technologies.
  • Based on the previous analysis and on both the WP2 evaluation and WP3 inputs, appropriate architecture of bit cell will be selected for complete integration in a CMOS process flow.
  • Mask definition with implementation of various FB-DRAM structures (memory cell, memory matrix and demonstrator) in terms of geometry, architecture and specific designs from WP4 in FD28 and FD14. Only the selected FB-DRAM structure will be considered for memory matrix.
  • Fabrication of three electrical wafer demonstrators with the selected FB-DRAM architecture including full integration up to reduced memory matrix and demonstrator. Morphological characterization as a complement to statistical characterization performed in WP1.

Role of partners

  • UGR: Design memory cells.
  • STM: Fabrication of memory cells in FD28 and FD14 technologies.
  • CEA: Fabrication of 3D Si memory cells. Evaluation of process modules.
  • INPG: Design of test devices.
  • IBM: Development of process modules for the III-V memory cell fabrication.
  • SureCore: Evaluation of the memory cell from a design perspective.

Interaction with other WPs

  • Provide devices for characterization to WP2.
  • Receive input for device optimization from WP2 and WP3.
  • Provide the technology for the memory matrix (WP4) and demonstrator (WP5).