REMINDER is divided into sixWork Packages, which are sub-divided into Tasks. The Tasks have detailed focus and well defined Deliverables. The deliverables are linked with the tasks and are listed in the Deliverables List.

work_plan
  • The work tasks in WP1, WP2, WP3 and WP4 follow a logical sequence in time and are interdependent.
  • WP5 is dedicated to the demonstration/test of developed eDRAM solution based on new Floating Body DRAMs, and the creation of a catalogue of potential end-user applications which could take advantage of the eDRAM solution developed on REMINDER.
  • WP6 is for management, dissemination and exploitation, and communication activities of the Consortium results.
  • WP2 is devoted to the development of specific methodologies for the experimental characterization of Floating Body-DRAM parameters, and to the investigation of memory cell performance and scalability. The experimental results obtained in WP2 will be used in WP3 (devoted to the simulation of the proposed devices) for the experimental validation of the numerical simulations, and for the fine calibration of different simulators. WP2 (experimental characterization) and WP3 (simulation) will also address the behaviour of the memory cells from variability and reliability point of view. Characterization of failures analysis will be performed at both device and circuit levels in WP2, and simulated in WP3.
  • Both experimental (WP2) and simulated (WP3) data will be used in WP4 for the elaboration of compact models of Floating Body DRAM cells, and for the design of a memory matrix specifically optimized for low-power consumption, variability immunity and reduced footprint. The inputs of WP2 and WP3, together with the designs of the memory matrix in WP4, will be also essential for the definition of the structures which will be fabricated in WP1.
  • WP1 will also take care of the fabrication of optimized memory cells in Extended and Beyond CMOS technologies (CEA-LETI).
  • Four series of memory structures will be studied along the project:
    • Run 0 (available non-optimized devices).
    • Run 1 (optimized memory cell and non-optimized memory matrix).
    • Run 2 (optimized memory matrix and a second set of optimized memory cell).
    • Run 3 for the fabrication of the memory demonstrator (test chip).

In a first stage, already available non-optimized devices will be operated as FBDRAM cells. These results will help to improve the characterization techniques (WP2) and to calibrate and validate the simulators (both home- made and commercial) (WP3). The experimental results on non-optimized devices, coupled with simulation results, will be useful for the selection of technology modules and ultra-scaled device architectures suitable for WP1. Although several devices or memory cells will be studied at this initial stage, only one of them will be retained for further development (optimized cell fabrication, memory matrix design and demonstration).

The selection will be made attending to the following items:

  • Experimental characterization and performance of available devices operated as FB-DRAM (WP1, WP2).
  • Advanced Electrical simulation of key parameters and performance of the different approaches. Only memory cells fullling the following criteria success will be retained. The bit-cell will be designed to fulll the following parameters:
    • Voltage range: 0.6-1V.
    • Random access: 150-500 Mhz.
    • Density: 8-10 Mb/mm2.
    • Static Power: 2-3 mW/Mb.
    • Retention time @125ºC: 100us to 1ms.
  • Variability study of the proposed devices. Threshold voltage, ON current and retention time distributions will be considered for the selection.
  • Analysis of the advanced process modules needed for the fabrication of the different approaches (WP1).

At M6, and taking into account the inputs of the items above, one preliminary selection of the memory bit cell among the three FB-DRAM candidates (A2RAM, MSDRAM and Z2FET) will be made. The memory cell selected will be used to design the pragmatic memory solution using FD28 and FD14 technologies and the memory demonstrator. This means that all efforts for the development of the compact models, auxiliary memory circuits, etc. will be limited to the selected FB-DRAM variant.

  • Run 1: Fabrication of optimized FB-DRAM solutions, (selected after benchmarking of Run 0 devices) and first approaches to the memory matrix in FD28.
  • Run 2: Results from the first run will educate the memory array design of the second run, which will be limited to the optimized version of the selected FBDRAM variant. In addition, a second set of optimized FB-DRAM cells will be fabricated taking into account the results of the rst run. In this Run, FD14 technology will be considered. In parallel to the pragmatic fabrication of the memory solutions in FD28 and FD14 technology (Run 1 and Run 2 above), optimized memory cells in Extended and Beyond CMOS technologies will be fabricated by CEA-LETI (3D Si nanowires) and IBM (III-V nanowires). The devices and structures fabricated in WP1 (Runs 0 to 2) will be carefully measured in WP2 and simulated in WP3, in order to extract the parameters of the compact models developed in WP4.
  • Run 3: The data will be useful to define end-user applications using the optimized memory solution and to fabricate the memory demonstrator (memory test chip) in Run 3.
No Title Leader Person Months Start Month End Month
WP1 Technology CEA/STM 99 1 30
WP2 Characterization INPG 106 1 36
WP3 Simulation GU 89 1 36
WP4 Modelling & Design GSS 85 4 36
WP5 Demostration & Benchmarking sureCore 40 18 33
WP6 Management, Dissemination, Communication & Exploitation UGR 35 1 36