The first pillar, memory cell
- the definition of the structure at theoretical level (concept), based on the characterization of existing devices
- extensive TCAD and advanced Multi-Subband Ensemble Monte Carlo simulation
- dedicated fabrication in FD28 and/or FD14 nm
- structural and electrical characterization
- optimization for low-power, variability, reliability and footprint
- modelling (physical and compact)
The final memory matrix demonstrator will be fabricated and the memory cell will be optimized for FDSOI. Nevertheless, the eventual replacement of Si by strained Si/SiGe and III-V materials in CMOS circuits, or the substitution of planar technologies by 3D integration for future technological nodes will require the redesign of dierent applications, including memory cells. For the sake of a better use of the resources, we will take advantage of the knowledge acquired during the optimization process of bit cells in planar FDSOI technology to develop FB-DRAM cells in 4 these emerging technologies.
We will also use the outcome of other EU projects such as III-V MOS, COMPOSE3, for the optimization of bit cells developed in pillar 1 in FD28 and FD14 technology nodes using these alternative materials. In order to achieve these goals, we will adopt a multiscale approach that enables us to determine the band structures and carrier transport in semiconductor NWs with different materials and geometries (Si, sSi, Si/Si-Ge core-shell, and III-V, and 3D integration). The fabrication of the different structures will be carried out by IBM in the case of III-V nanowires, and CEA in the case of Si NWs and 3D integration. A similar scheme to the one adopted in the case of planar technologies will be followed in this “Beyond and Extended CMOS” research.
The second pillar: memory matrix
The information provided by the first pillar will be used to design the memory matrix in planar FD28 and FD14 STMicroelectronics technology with special attention to ultralow-power consumption, reduced variability and minimized footprint.
The third pillar: memory exploitation
Two important tasks are then foreseen in the third pillar of this proposal to contribute to this leadership:
- Implementation of a test chip using the embedded memory solution for IoT applications, and benchmarking with other emerging memory solutions.
- Market study and elaboration of a catalogue of potential applications.