REMINDER is ultimately focused to develop an embedded DRAM solution for IoT cutedge devices, i.e. the pursued memory block will be optimized for ultra-low-power consumption, variability immunity, and low cost, in addition to the footprint miniaturization.

The pragmatic approach for quick lab-to-market demonstration is to use the established FDSOI technology, without introducing alternative materials or new steps in the fabrication process (different from the ones already necessary to fabricate the rest of blocks in the system).

In parallel, we will also define longer-term FB-DRAM solutions using emerging technologies that are not yet stabilized (III-V), NWs, and SiGe).

To achieve the objectives of REMINDER, the project structure is founded on the three main pillars.

The first pillar, memory cell

The first pillar is focused on the investigation of the bit cell, which is the fundamental building unit of the memory block. The memory cell is an electronic circuit that stores one bit of binary information and it must be set to store a logic ‘1’ and reset to store a logic ‘0’. This value is maintained/stored until the set/reset process changes it, and the information is accessed during the reading process. The investigation of the memory cell carried out in this first pillar embraces:

  • the definition of the structure at theoretical level (concept), based on the characterization of existing devices
  • extensive TCAD and advanced Multi-Subband Ensemble Monte Carlo simulation
  • dedicated fabrication in FD28 and/or FD14 nm
  • structural and electrical characterization
  • optimization for low-power, variability, reliability and footprint
  • modelling (physical and compact)

All the steps above will be integrated in a loop-based scheme. Already available devices at M1 (starting of the project) will be used to calibrate the simulators, to tune the characterization tools, and optimize the proposed bit cells (A2RAM, MSDRAM and Z2-FET). This information will be used to design optimized bit cells, which will be fabricated in a first lot at STMicroelectronics. The fabricated optimized bit cells, will be characterized, simulated and the compact models will be obtained for circuit simulation.

first-pillar

The final memory matrix demonstrator will be fabricated and the memory cell will be optimized for FDSOI. Nevertheless, the eventual replacement of Si by strained Si/SiGe and III-V materials in CMOS circuits, or the substitution of planar technologies by 3D integration for future technological nodes will require the redesign of dierent applications, including memory cells. For the sake of a better use of the resources, we will take advantage of the knowledge acquired during the optimization process of bit cells in planar FDSOI technology to develop FB-DRAM cells in 4 these emerging technologies.

We will also use the outcome of other EU projects such as III-V MOS, COMPOSE3, for the optimization of bit cells developed in pillar 1 in FD28 and FD14 technology nodes using these alternative materials. In order to achieve these goals, we will adopt a multiscale approach that enables us to determine the band structures and carrier transport in semiconductor NWs with different materials and geometries (Si, sSi, Si/Si-Ge core-shell, and III-V, and 3D integration). The fabrication of the different structures will be carried out by IBM in the case of III-V nanowires, and CEA in the case of Si NWs and 3D integration. A  similar scheme to the one adopted in the case of planar technologies will be followed in this “Beyond and Extended CMOS” research.

The second pillar: memory matrix

The information provided by the first pillar will be used to design the memory matrix in planar FD28 and FD14 STMicroelectronics technology with special attention to ultralow-power consumption, reduced variability and minimized footprint.

second-pillar

The memory sub-circuits, blocks and architectures will be carefully analysed from the power-consumption point of view and the subsequent application of variability tolerant design techniques underpinned by variability analysis and statistical simulation technology. The design will be leaded by SureCore and GSS, but it will also take advantage of the participation of STM and the invaluable contribution of KIST, the Korean Institute of Science and Technology.

Once the memory matrix has been designed, simulated and optimized, it will be fabricated by STMicroelectronics using their FD28 and FD14 technology. The fabricated memory matrix will then be characterized by STM and KIST, including variability and reliability studies. Characterization of failure modes at extremely accelerating conditions of the memory cells will be performed by KIST.

The third pillar: memory exploitation

REMINDER last goal is the exploitation of the embedded memory solution in end-user applications, thus keeping the industrial leadership of Europe in planar FDSOI technology. During the last ve years, through different European projects like Dynamic-ULP (EUREKA label) and Reaching22 (CATRENE) or PLACES2BE (ENIAC), or recently WAYTOGO FAST (ECSEL) the FDSOI UTBB ecosystem has enlarged in Europe (and everywhere) and its credibility was strongly reinforced through the achievement of successful demonstrators and innovative technologies.

European electronic industry, at the root of this technology, has demonstrated its capacity to produce a new standard, play a key role in the More Moore’s law, and construct a worldwide consortium promoting and pushing the adoption of an innovative enabling technology.

third-pillar

Two important tasks are then foreseen in the third pillar of this proposal to contribute to this leadership:

  • Implementation of a test chip using the embedded memory solution for IoT applications, and benchmarking with other emerging memory solutions.
  • Market study and elaboration of a catalogue of potential applications.