REMINDER aims to develop an embedded DRAM solution optimized for ultra-lowpower consumption and variability immunity, specically focused on Internet of Things cut-edge devices. REMINDER is based on three pillars:

Investigation

Investigation (concept, design, characterization, simulation, modelling), selection and optimization of a Floating-Body memory bit cell in terms of low power and low voltage, high reliability, robustness (variability), speed, reduced footprint and cost. Fabrication of selected bit cells with FDSOI and III-V technologies.

Design and Fabrication

Design and fabrication in FDSOI 28nm (FD28) and FDSOI 14nm (FD14) technology nodes of a memory matrix based on the optimized bit-cells developed in the first pillar. Matrix memory sub-circuits, blocks and architectures will be carefully analysed from the power-consumption point of view. In addition variability tolerant design techniques underpinned by variability analysis and statistical simulation technology will be considered.

Demostration

Demonstration of a system on chip (SoC) application using the developed memory solution and benchmarking with alternative embedded memory blocks.

REMINDER "three pillars"

three pillars

The eventual replacement of Si by strained Si/SiGe and III-V materials in future CMOS circuits would also require the redesign of different applications, including memory cells, and therefore we also propose the evaluation of the optimized bit cells developed in pillar i) in FD28 and FD14 technology nodes using these alternative materials. In order to achieve these goals, we adopt a multiscale approach that enables us to determine the band structures and the memory mechanisms (Band-to-Band Tunnelling, carrier transport and generation-recombination) in semiconductor NWs with different materials and geometries (Si, sSi, Si/Si-Ge core-shell, and III-V).We will employ numerical tools at different levels from atomic-detail (DFT) to the effective mass approximation.

Collaterally, the fullment of the objectives above will also imply the development of:

  • New techniques for the electrical characterization of ultimate CMOS nanometric devices. This will allow us to improve the CMOS technology by boosting device performance.
  • New behavioural models, incorporating variability effects, to reach a deep understanding of nanoelectronics devices.
  • Advanced simulation tools for nanoelectronic devices for state of the art, and emerging devices.
  • Extreme low power solutions.