REMINDER aims to develop an embedded DRAM solution optimized for ultra-low power consumption and variability immunity, specifically focused on Internet of Things cut-edge devices, wearable and health systems. The objectives of REMINDER are defined to 1) demonstrate the proof of concept of the embedded DRAM optimized for Performance-Power-Area-Cost constrains, and 2) address the challenges associated with the key technologies underlying the concept.

Therefore, three different types of objectives are considered: technical, scientific and strategic. The scientific and technical objectives are defined to demonstrate at different levels (bit cell, memory matrix, and SoC) the pragmatic implementation of an embedded DRAM solution. The strategic objectives aim to contribute to the strengthening of the industrialization of the FDSOI technology by designing new products, and to advance in the maturation of emerging CMOS technologies (III-V, nanowires, 3D integration) and therefore to demonstrate the long term impact of REMINDER proposal.

Technical objectives

  • Tech 1: Investigation (concept, characterization, simulation, modelling), selection and optimization of a memory bit cell in terms of low power and low voltage, high reliability, robustness (variability), speed, reduced footprint and cost based on Floating-Body SOI concept. Fabrication of optimized bit cells and benchmark with other DRAMs.
  • Tech 2: Design and fabrication in FD28 and FD14 technology nodes of a memory matrix based on the optimized bit-cells. Matrix memory sub-circuits, blocks and architectures will be carefully analysed from the power-consumption point of view. In addition variability tolerant design techniques underpinned by variability analysis and statistical simulation technology will be considered.
  • Tech 3: Demonstration of the developed memory solution and benchmarking with alternative embedded memory blocks.

Scientific objectives

  • Sci 1: Electrical characterization of nanoelectronic devices: from ultimate CMOS to Beyond Si CMOS.
  • Sci 2: Advanced numerical simulation: Top-down hierarchical simulation.
  • Sci 3: Variability and reliability issues of advanced nanodevices.
  • Sci 4: Development of ultra-low power memory solutions.

Strategic objectives

  • Stra 1: Reinforce the European manufacturing position by gaining leadership through the demonstration of ultra-low-power IP blocks for IoT edge devices, wearables and health systems using FDSOI technologies developed by STMicroelectronics.
  • Stra 2: Demonstrate the suitability of emerging III-V MOSFETs, nanowires FETs (Si, III-V, SiGe) and 3D circuits for ultralow-power applications, extending the FDSOI technology.
  • Stra 3: Given the strategic importance of the emerging IoT market on Governments, Economies, and Industry, this project will deliver significant strategic benefit to the partners and the EU through the research and delivery of a new memory solution which will offer competitive advantage to EU companies by:
  • Improved performance, specifically lower power.
  • Lower cost, specifically through a simpler process and smaller area.