Work Package 1
- D1.1 – Description of the technical requirements for advanced process modules to be included in first run.
- D1.2 – CMOS Lot primary characterization.
- D1.3 – Evaluation of memory cells from design perspective
- D1.4 – Fabrication of FB-DRAM memory cells using Si nanowires, and 3D integration
- D1.5 – Integration and fabrication of FB-DRAM cells using III-V nanowires
- D1.6 – CMOS Lot primary characterization (updated version of D1.2 at M24)
- D1.7 – CMOS Lot primary characterization (updated version of D1.2 at M42)
Work Package 2
- D2.1 – Definition of the electrical parameters required by the simulation and modelling.
- D2.2 – Development of new characterization techniques for the extraction of “transient” parameters and memory performance.
- D2.3 – Extraction of the physics parameters needed in compact models and design.
- D2.4 – Characterization of III-V nanowires and devices
- D2.5 – Characterization of optimized FB-DRAMs fabricated in the first run of WP1 in FD28
- D2.6 – Low power DRAM architecture specification and preliminary datasheet
- D2.7 – Characterization of the optimized FB-DRAM in the second run of
WP1 in FD14
- D2.8 – Functional characterization of the memory matrix
- D2.9 – Characterization of failure modes at extremely accelerating conditions
- D2.10 – Characterization of optimized FB-DRAM for sub-14nm technological nodes
Work Package 3
- D3.1 – Definition of the electrical parameters required by the simulation and modelling.
- D3.2 – Development of new characterization techniques for the extraction of “transient” parameters and memory performance.
- D3.3 – Implementation of the novel FB- DRAM generic structures in 2D TCAD simulators.
- D3.4 – Simulation of FB-DRAM variability using DOE and surface response techniques.
- D3.5 – Development of accurate models to describe band structure related effects in III-V nanowires.
- D3.6 – Development of the simulation methodology for conducting detailed transient analysis and systematic results.
- D3.7 – FB-DRAM optimization for the second fabrication run.
- D3.8 – Calibration of the 3DMSEMC simulator: FinFET, SiNW and FB-DRAM benchmarking
- D3.9 – Development of new simulation tools: Multisubband Monte Carlo
- D3.10 – Carrier transport in III-V nanowires: Development of scattering mechanisms and 3DMS-EMC integration
- D3.11 – Advanced physical simulation and optimization of FBDRAM cells using 3DMSEMC tools.
Work Package 4
- D4.1 – Technical requirements for the modelling platform.
- D4.2 – Compact models and assessment of the model accuracy based on comparison of simulation and measurement results.
- D4.3 – Plug and play library with advanced toolbox for integration of FBDRAM devices.
- D4.4 – Spice macro compact model for selected FD_DRAM cell structure
- D4.5 – Complete embedded
Work Package 5
- D5.1 – Comparison data to ReRAM and Magnetic memories
- D5.2 – List of detailed end-user applications
- D5.3 – Margining Report
- D5.4 – Embedded FB-DRAM memory compiler
- D5.5 – Technical specifications of targeted application and benchmark results
- D5.6 – Test chip samples & evaluation report
Work Package 6
- D6.1 – REMINDER website.
- D6.2 – REMINDER Data Management Plan.
- D6.3 – First year technical report
- D6.4 – First REMINDER Industrial workshop
- D6.5 – Second year technical report
- D6.6 – Second REMINDER Industrial workshop
- D6.7 – Final report
- D6.8 – List of dissemination and training actions to promote REMINDER research
- D6.9 – Report on Communication activities
- D6.10 – List of networking activities to promote REMINDER research